Equations

********** Mapped Logic **********
FDCPE_XLXI_14/Q0: FDCPE port map (XLXI_14/Q(0),XLXI_14/Q_D(0),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(0) <= (XLXN_18(0) AND load/load_D2);
FDCPE_XLXI_14/Q1: FDCPE port map (XLXI_14/Q(1),XLXI_14/Q_D(1),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(1) <= ((XLXN_18(1) AND load/load_D2)
      OR (XLXI_14/Q(0) AND NOT load/load_D2));
FDCPE_XLXI_14/Q2: FDCPE port map (XLXI_14/Q(2),XLXI_14/Q_D(2),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(2) <= ((XLXN_18(2) AND load/load_D2)
      OR (XLXI_14/Q(1) AND NOT load/load_D2));
FDCPE_XLXI_14/Q3: FDCPE port map (XLXI_14/Q(3),XLXI_14/Q_D(3),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(3) <= ((XLXN_18(3) AND load/load_D2)
      OR (XLXI_14/Q(2) AND NOT load/load_D2));
FDCPE_XLXI_14/Q4: FDCPE port map (XLXI_14/Q(4),XLXI_14/Q_D(4),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(4) <= ((XLXN_18(4) AND load/load_D2)
      OR (XLXI_14/Q(3) AND NOT load/load_D2));
FDCPE_XLXI_14/Q5: FDCPE port map (XLXI_14/Q(5),XLXI_14/Q_D(5),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(5) <= ((XLXN_18(5) AND load/load_D2)
      OR (XLXI_14/Q(4) AND NOT load/load_D2));
FDCPE_XLXI_14/Q6: FDCPE port map (XLXI_14/Q(6),XLXI_14/Q_D(6),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(6) <= ((XLXN_18(6) AND load/load_D2)
      OR (XLXI_14/Q(5) AND NOT load/load_D2));
FDCPE_XLXI_14/Q7: FDCPE port map (XLXI_14/Q(7),XLXI_14/Q_D(7),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(7) <= ((XLXN_18(7) AND load/load_D2)
      OR (XLXI_14/Q(6) AND NOT load/load_D2));
FDCPE_XLXI_14/Q8: FDCPE port map (XLXI_14/Q(8),XLXI_14/Q_D(8),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(8) <= ((XLXN_18(8) AND load/load_D2)
      OR (XLXI_14/Q(7) AND NOT load/load_D2));
FDCPE_XLXI_14/Q9: FDCPE port map (XLXI_14/Q(9),XLXI_14/Q_D(9),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(9) <= ((XLXN_18(9) AND load/load_D2)
      OR (XLXI_14/Q(8) AND NOT load/load_D2));
FDCPE_XLXI_14/Q10: FDCPE port map (XLXI_14/Q(10),XLXI_14/Q_D(10),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(10) <= ((XLXN_18(10) AND load/load_D2)
      OR (XLXI_14/Q(9) AND NOT load/load_D2));
FDCPE_XLXI_14/Q11: FDCPE port map (XLXI_14/Q(11),XLXI_14/Q_D(11),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(11) <= ((XLXN_18(11) AND load/load_D2)
      OR (XLXI_14/Q(10) AND NOT load/load_D2));
FDCPE_XLXI_14/Q12: FDCPE port map (XLXI_14/Q(12),XLXI_14/Q_D(12),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(12) <= ((XLXN_18(12) AND load/load_D2)
      OR (XLXI_14/Q(11) AND NOT load/load_D2));
FDCPE_XLXI_14/Q13: FDCPE port map (XLXI_14/Q(13),XLXI_14/Q_D(13),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(13) <= ((XLXN_18(13) AND load/load_D2)
      OR (XLXI_14/Q(12) AND NOT load/load_D2));
FDCPE_XLXI_14/Q14: FDCPE port map (XLXI_14/Q(14),XLXI_14/Q_D(14),clk_spi,'0','0',ce_spi);
     XLXI_14/Q_D(14) <= ((XLXN_18(14) AND load/load_D2)
      OR (XLXI_14/Q(13) AND NOT load/load_D2));
FTCPE_XLXN_180: FTCPE port map (XLXN_18(0),'1',clk,reset,'0',XLXN_18_CE(0));
     XLXN_18_CE(0) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_181: FTCPE port map (XLXN_18(1),XLXN_18(0),clk,reset,'0',XLXN_18_CE(1));
     XLXN_18_CE(1) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_182: FTCPE port map (XLXN_18(2),XLXN_18_T(2),clk,reset,'0',XLXN_18_CE(2));
     XLXN_18_T(2) <= (XLXN_18(0) AND XLXN_18(1));
     XLXN_18_CE(2) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_183: FTCPE port map (XLXN_18(3),XLXN_18_T(3),clk,reset,'0',XLXN_18_CE(3));
     XLXN_18_T(3) <= (XLXN_18(0) AND XLXN_18(1) AND XLXN_18(2));
     XLXN_18_CE(3) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_184: FTCPE port map (XLXN_18(4),XLXN_18_T(4),clk,reset,'0',XLXN_18_CE(4));
     XLXN_18_T(4) <= (XLXN_18(0) AND XLXN_18(1) AND XLXN_18(2) AND
      XLXN_18(3));
     XLXN_18_CE(4) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_185: FTCPE port map (XLXN_18(5),XLXN_18_T(5),clk,reset,'0',XLXN_18_CE(5));
     XLXN_18_T(5) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(1) AND
      XLXN_18(2) AND XLXN_18(3));
     XLXN_18_CE(5) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_186: FTCPE port map (XLXN_18(6),XLXN_18_T(6),clk,reset,'0',XLXN_18_CE(6));
     XLXN_18_T(6) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(1) AND
      XLXN_18(5) AND XLXN_18(2) AND XLXN_18(3));
     XLXN_18_CE(6) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_187: FTCPE port map (XLXN_18(7),XLXN_18_T(7),clk,reset,'0',XLXN_18_CE(7));
     XLXN_18_T(7) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(1) AND
      XLXN_18(5) AND XLXN_18(2) AND XLXN_18(6) AND XLXN_18(3));
     XLXN_18_CE(7) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_188: FTCPE port map (XLXN_18(8),XLXN_18_T(8),clk,reset,'0',XLXN_18_CE(8));
     XLXN_18_T(8) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(1) AND
      XLXN_18(5) AND XLXN_18(2) AND XLXN_18(6) AND XLXN_18(3) AND
      XLXN_18(7));
     XLXN_18_CE(8) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_189: FTCPE port map (XLXN_18(9),XLXN_18_T(9),clk,reset,'0',XLXN_18_CE(9));
     XLXN_18_T(9) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND
      XLXN_18(1) AND XLXN_18(5) AND XLXN_18(2) AND XLXN_18(6) AND
      XLXN_18(3) AND XLXN_18(7));
     XLXN_18_CE(9) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_1810: FTCPE port map (XLXN_18(10),XLXN_18_T(10),clk,reset,'0',XLXN_18_CE(10));
     XLXN_18_T(10) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND
      XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND XLXN_18(2) AND
      XLXN_18(6) AND XLXN_18(3) AND XLXN_18(7));
     XLXN_18_CE(10) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_1811: FTCPE port map (XLXN_18(11),XLXN_18_T(11),clk,reset,'0',XLXN_18_CE(11));
     XLXN_18_T(11) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND
      XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND XLXN_18(10) AND
      XLXN_18(2) AND XLXN_18(6) AND XLXN_18(3) AND XLXN_18(7));
     XLXN_18_CE(11) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_1812: FTCPE port map (XLXN_18(12),XLXN_18_T(12),clk,reset,'0',XLXN_18_CE(12));
     XLXN_18_T(12) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND
      XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND XLXN_18(10) AND
      XLXN_18(2) AND XLXN_18(6) AND XLXN_18(11) AND XLXN_18(3) AND
      XLXN_18(7));
     XLXN_18_CE(12) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_1813: FTCPE port map (XLXN_18(13),XLXN_18_T(13),clk,reset,'0',XLXN_18_CE(13));
     XLXN_18_T(13) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND
      XLXN_18(12) AND XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND
      XLXN_18(10) AND XLXN_18(2) AND XLXN_18(6) AND XLXN_18(11) AND
      XLXN_18(3) AND XLXN_18(7));
     XLXN_18_CE(13) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_1814: FTCPE port map (XLXN_18(14),XLXN_18_T(14),clk,reset,'0',XLXN_18_CE(14));
     XLXN_18_T(14) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND
      XLXN_18(12) AND XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND
      XLXN_18(10) AND XLXN_18(13) AND XLXN_18(2) AND XLXN_18(6) AND
      XLXN_18(11) AND XLXN_18(3) AND XLXN_18(7));
     XLXN_18_CE(14) <= (XLXN_4 AND NOT XLXN_5);
FTCPE_XLXN_1815: FTCPE port map (XLXN_18(15),XLXN_18_T(15),clk,reset,'0',XLXN_18_CE(15));
     XLXN_18_T(15) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND
      XLXN_18(12) AND XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND
      XLXN_18(10) AND XLXN_18(13) AND XLXN_18(2) AND XLXN_18(6) AND
      XLXN_18(11) AND XLXN_18(14) AND XLXN_18(3) AND XLXN_18(7));
     XLXN_18_CE(15) <= (XLXN_4 AND NOT XLXN_5);
FDCPE_XLXN_26: FDCPE port map (XLXN_26,ce_spi,clk_spi,'0','0');
FDCPE_XLXN_4: FDCPE port map (XLXN_4,'0','0',reset,start);
FDCPE_XLXN_5: FDCPE port map (XLXN_5,'0','0',reset,stop);
FDCPE_dat_spi: FDCPE port map (dat_spi,dat_spi_D,clk_spi,'0','0',ce_spi);
     dat_spi_D <= ((XLXN_18(15) AND load/load_D2)
      OR (XLXI_14/Q(14) AND NOT load/load_D2));
load/load_D2 <= (ce_spi AND NOT XLXN_26);
FDCPE_reset: FDCPE port map (reset,load/load_D2,clk_spi,'0','0');
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);