cpldfit:  version O.61xd                            Xilinx Inc.
                                  Fitter Report
Design Name: first_project_top                   Date:  1-12-2013,  9:11PM
Device Used: XC95288XL-10-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
37 /288 ( 13%) 101 /1440 (  7%) 65 /864 (  8%)   36 /288 ( 12%) 6  /117 (  5%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           9/18       18/54       27/90       0/ 8
FB2           8/18       18/54       24/90       0/10
FB3          14/18       17/54       36/90       5/ 5*
FB4           6/18       12/54       14/90       0/ 6
FB5           0/18        0/54        0/90       1/ 8
FB6           0/18        0/54        0/90       0/ 8
FB7           0/18        0/54        0/90       0/ 4
FB8           0/18        0/54        0/90       0/ 5
FB9           0/18        0/54        0/90       0/ 9
FB10          0/18        0/54        0/90       0/10
FB11          0/18        0/54        0/90       0/ 7
FB12          0/18        0/54        0/90       0/ 6
FB13          0/18        0/54        0/90       0/ 6
FB14          0/18        0/54        0/90       0/ 8
FB15          0/18        0/54        0/90       0/ 9
FB16          0/18        0/54        0/90       0/ 8
             -----       -----       -----      -----    
             37/288      65/864     101/1440     6/117

* - Resource is exhausted

** Global Control Resources **

Signal 'clk' mapped onto global clock net GCK1.
Signal 'clk_spi' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :     4     109
Output        :    1           1    |  GCK/IO           :     2       3
Bidirectional :    0           0    |  GTS/IO           :     0       4
GCK           :    2           2    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      6           6

** Power Data **

There are 37 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'first_project_top.ise'.
INFO:Cpld - Inferring BUFG constraint for signal 'clk' based upon the LOC
   constraint 'P30'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'clk_spi' based upon the LOC
   constraint 'P32'. It is recommended that you declare this BUFG explicitedly
   in your design. Note that for certain device families the output of a BUFG
   constraint can not drive a gated clock, and the BUFG constraint will be
   ignored.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS_clk_spi =
   PERIOD:clk_spi:500.000nS:HIGH:250.000nS because of one of the following: (a)
   a signal name was not found; (b) a signal was removed or renamed due to
   optimization; (c) there is no path between the FROM node and TO node in the
   TIMESPEC.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS_clk_100 =
   PERIOD:clk_100:10.000nS:HIGH:5.000nS because of one of the following: (a) a
   signal name was not found; (b) a signal was removed or renamed due to
   optimization; (c) there is no path between the FROM node and TO node in the
   TIMESPEC.
*************************  Summary of Mapped Logic  ************************

** 1 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
dat_spi             3     4     FB3_12  31   I/O     O       STD  SLOW RESET

** 36 Buried Nodes **

Signal              Total Total Loc     Pwr  Reg Init
Name                Pts   Inps          Mode State
XLXN_18<9>          3     12    FB1_10  STD  RESET
XLXN_18<8>          3     11    FB1_11  STD  RESET
XLXN_18<7>          3     10    FB1_12  STD  RESET
XLXN_18<15>         3     18    FB1_13  STD  RESET
XLXN_18<14>         3     17    FB1_14  STD  RESET
XLXN_18<13>         3     16    FB1_15  STD  RESET
XLXN_18<12>         3     15    FB1_16  STD  RESET
XLXN_18<11>         3     14    FB1_17  STD  RESET
XLXN_18<10>         3     13    FB1_18  STD  RESET
XLXI_14/Q<5>        3     4     FB2_11  STD  RESET
XLXI_14/Q<2>        3     4     FB2_12  STD  RESET
XLXI_14/Q<1>        3     4     FB2_13  STD  RESET
XLXI_14/Q<14>       3     4     FB2_14  STD  RESET
XLXI_14/Q<13>       3     4     FB2_15  STD  RESET
XLXI_14/Q<12>       3     4     FB2_16  STD  RESET
XLXI_14/Q<11>       3     4     FB2_17  STD  RESET
XLXI_14/Q<10>       3     4     FB2_18  STD  RESET
reset               1     1     FB3_5   STD  RESET
XLXN_26             1     1     FB3_6   STD  RESET
XLXN_18<0>          2     3     FB3_7   STD  RESET
XLXI_14/Q<0>        2     3     FB3_8   STD  RESET
XLXN_18<6>          3     9     FB3_9   STD  RESET
XLXN_18<5>          3     8     FB3_10  STD  RESET
XLXN_18<4>          3     7     FB3_11  STD  RESET
XLXN_18<3>          3     6     FB3_13  STD  RESET
XLXN_18<2>          3     5     FB3_14  STD  RESET
XLXN_18<1>          3     4     FB3_15  STD  RESET
XLXI_14/Q<9>        3     4     FB3_16  STD  RESET
XLXI_14/Q<4>        3     4     FB3_17  STD  RESET
XLXI_14/Q<3>        3     4     FB3_18  STD  RESET
load/load_D2        1     2     FB4_13  STD  
XLXN_5              2     2     FB4_14  STD  RESET
XLXN_4              2     2     FB4_15  STD  RESET
XLXI_14/Q<8>        3     4     FB4_16  STD  RESET
XLXI_14/Q<7>        3     4     FB4_17  STD  RESET
XLXI_14/Q<6>        3     4     FB4_18  STD  RESET

** 5 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
ce_spi              FB3_2   28   I/O     I
clk                 FB3_10  30   GCK/I/O GCK
clk_spi             FB3_14  32   GCK/I/O GCK
start               FB3_15  33   I/O     I
stop                FB5_2   34   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               18/36
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2         (b)     
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
(unused)              0       0     0   5     FB1_5   20    I/O     
(unused)              0       0     0   5     FB1_6   21    I/O     
(unused)              0       0     0   5     FB1_7         (b)     
(unused)              0       0     0   5     FB1_8   22    I/O     
(unused)              0       0     0   5     FB1_9         (b)     
XLXN_18<9>            3       0     0   2     FB1_10  23    I/O     (b)
XLXN_18<8>            3       0     0   2     FB1_11        (b)     (b)
XLXN_18<7>            3       0     0   2     FB1_12  24    I/O     (b)
XLXN_18<15>           3       0     0   2     FB1_13        (b)     (b)
XLXN_18<14>           3       0     0   2     FB1_14  25    I/O     (b)
XLXN_18<13>           3       0     0   2     FB1_15  26    I/O     (b)
XLXN_18<12>           3       0     0   2     FB1_16        (b)     (b)
XLXN_18<11>           3       0     0   2     FB1_17  27    I/O     (b)
XLXN_18<10>           3       0     0   2     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: XLXN_18<0>         7: XLXN_18<1>        13: XLXN_18<7> 
  2: XLXN_18<10>        8: XLXN_18<2>        14: XLXN_18<8> 
  3: XLXN_18<11>        9: XLXN_18<3>        15: XLXN_18<9> 
  4: XLXN_18<12>       10: XLXN_18<4>        16: XLXN_4 
  5: XLXN_18<13>       11: XLXN_18<5>        17: XLXN_5 
  6: XLXN_18<14>       12: XLXN_18<6>        18: reset 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXN_18<9>           X.....XXXXXXXX.XXX...................... 12
XLXN_18<8>           X.....XXXXXXX..XXX...................... 11
XLXN_18<7>           X.....XXXXXX...XXX...................... 10
XLXN_18<15>          XXXXXXXXXXXXXXXXXX...................... 18
XLXN_18<14>          XXXXX.XXXXXXXXXXXX...................... 17
XLXN_18<13>          XXXX..XXXXXXXXXXXX...................... 16
XLXN_18<12>          XXX...XXXXXXXXXXXX...................... 15
XLXN_18<11>          XX....XXXXXXXXXXXX...................... 14
XLXN_18<10>          X.....XXXXXXXXXXXX...................... 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               18/36
Number of signals used by logic mapping into function block:  18
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
(unused)              0       0     0   5     FB2_2   9     I/O     
(unused)              0       0     0   5     FB2_3   10    I/O     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   11    I/O     
(unused)              0       0     0   5     FB2_6   12    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   13    I/O     
(unused)              0       0     0   5     FB2_9         (b)     
(unused)              0       0     0   5     FB2_10  14    I/O     
XLXI_14/Q<5>          3       0     0   2     FB2_11        (b)     (b)
XLXI_14/Q<2>          3       0     0   2     FB2_12  15    I/O     (b)
XLXI_14/Q<1>          3       0     0   2     FB2_13        (b)     (b)
XLXI_14/Q<14>         3       0     0   2     FB2_14  16    I/O     (b)
XLXI_14/Q<13>         3       0     0   2     FB2_15  17    I/O     (b)
XLXI_14/Q<12>         3       0     0   2     FB2_16        (b)     (b)
XLXI_14/Q<11>         3       0     0   2     FB2_17  19    I/O     (b)
XLXI_14/Q<10>         3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: XLXI_14/Q<0>       7: XLXI_14/Q<4>      13: XLXN_18<14> 
  2: XLXI_14/Q<10>      8: XLXI_14/Q<9>      14: XLXN_18<1> 
  3: XLXI_14/Q<11>      9: XLXN_18<10>       15: XLXN_18<2> 
  4: XLXI_14/Q<12>     10: XLXN_18<11>       16: XLXN_18<5> 
  5: XLXI_14/Q<13>     11: XLXN_18<12>       17: ce_spi 
  6: XLXI_14/Q<1>      12: XLXN_18<13>       18: load/load_D2 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXI_14/Q<5>         ......X........XXX...................... 4
XLXI_14/Q<2>         .....X........X.XX...................... 4
XLXI_14/Q<1>         X............X..XX...................... 4
XLXI_14/Q<14>        ....X.......X...XX...................... 4
XLXI_14/Q<13>        ...X.......X....XX...................... 4
XLXI_14/Q<12>        ..X.......X.....XX...................... 4
XLXI_14/Q<11>        .X.......X......XX...................... 4
XLXI_14/Q<10>        .......XX.......XX...................... 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               17/37
Number of signals used by logic mapping into function block:  17
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
(unused)              0       0     0   5     FB3_2   28    I/O     I
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
reset                 1       0     0   4     FB3_5         (b)     (b)
XLXN_26               1       0     0   4     FB3_6         (b)     (b)
XLXN_18<0>            2       0     0   3     FB3_7         (b)     (b)
XLXI_14/Q<0>          2       0     0   3     FB3_8         (b)     (b)
XLXN_18<6>            3       0     0   2     FB3_9         (b)     (b)
XLXN_18<5>            3       0     0   2     FB3_10  30    GCK/I/O GCK
XLXN_18<4>            3       0     0   2     FB3_11        (b)     (b)
dat_spi               3       0     0   2     FB3_12  31    I/O     O
XLXN_18<3>            3       0     0   2     FB3_13        (b)     (b)
XLXN_18<2>            3       0     0   2     FB3_14  32    GCK/I/O GCK
XLXN_18<1>            3       0     0   2     FB3_15  33    I/O     I
XLXI_14/Q<9>          3       0     0   2     FB3_16        (b)     (b)
XLXI_14/Q<4>          3       0     0   2     FB3_17        (b)     (b)
XLXI_14/Q<3>          3       0     0   2     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: XLXI_14/Q<14>      7: XLXN_18<1>        13: XLXN_4 
  2: XLXI_14/Q<2>       8: XLXN_18<2>        14: XLXN_5 
  3: XLXI_14/Q<3>       9: XLXN_18<3>        15: ce_spi 
  4: XLXI_14/Q<8>      10: XLXN_18<4>        16: load/load_D2 
  5: XLXN_18<0>        11: XLXN_18<5>        17: reset 
  6: XLXN_18<15>       12: XLXN_18<9>       

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
reset                ...............X........................ 1
XLXN_26              ..............X......................... 1
XLXN_18<0>           ............XX..X....................... 3
XLXI_14/Q<0>         ....X.........XX........................ 3
XLXN_18<6>           ....X.XXXXX.XX..X....................... 9
XLXN_18<5>           ....X.XXXX..XX..X....................... 8
XLXN_18<4>           ....X.XXX...XX..X....................... 7
dat_spi              X....X........XX........................ 4
XLXN_18<3>           ....X.XX....XX..X....................... 6
XLXN_18<2>           ....X.X.....XX..X....................... 5
XLXN_18<1>           ....X.......XX..X....................... 4
XLXI_14/Q<9>         ...X.......X..XX........................ 4
XLXI_14/Q<4>         ..X......X....XX........................ 4
XLXI_14/Q<3>         .X......X.....XX........................ 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               12/42
Number of signals used by logic mapping into function block:  12
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   2     GTS/I/O 
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
(unused)              0       0     0   5     FB4_5   3     GTS/I/O 
(unused)              0       0     0   5     FB4_6   4     I/O     
(unused)              0       0     0   5     FB4_7         (b)     
(unused)              0       0     0   5     FB4_8   5     GTS/I/O 
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11        (b)     
(unused)              0       0     0   5     FB4_12  6     GTS/I/O 
load/load_D2          1       0     0   4     FB4_13        (b)     (b)
XLXN_5                2       0     0   3     FB4_14  7     I/O     (b)
XLXN_4                2       0     0   3     FB4_15        (b)     (b)
XLXI_14/Q<8>          3       0     0   2     FB4_16        (b)     (b)
XLXI_14/Q<7>          3       0     0   2     FB4_17        (b)     (b)
XLXI_14/Q<6>          3       0     0   2     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: XLXI_14/Q<5>       5: XLXN_18<7>         9: load/load_D2 
  2: XLXI_14/Q<6>       6: XLXN_18<8>        10: reset 
  3: XLXI_14/Q<7>       7: XLXN_26           11: start 
  4: XLXN_18<6>         8: ce_spi            12: stop 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
load/load_D2         ......XX................................ 2
XLXN_5               .........X.X............................ 2
XLXN_4               .........XX............................. 2
XLXI_14/Q<8>         ..X..X.XX............................... 4
XLXI_14/Q<7>         .X..X..XX............................... 4
XLXI_14/Q<6>         X..X...XX............................... 4
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB5_1         (b)     
(unused)              0       0     0   5     FB5_2   34    I/O     I
(unused)              0       0     0   5     FB5_3         (b)     
(unused)              0       0     0   5     FB5_4         (b)     
(unused)              0       0     0   5     FB5_5   35    I/O     
(unused)              0       0     0   5     FB5_6         (b)     
(unused)              0       0     0   5     FB5_7         (b)     
(unused)              0       0     0   5     FB5_8   38    GCK/I/O 
(unused)              0       0     0   5     FB5_9         (b)     
(unused)              0       0     0   5     FB5_10  39    I/O     
(unused)              0       0     0   5     FB5_11        (b)     
(unused)              0       0     0   5     FB5_12  40    I/O     
(unused)              0       0     0   5     FB5_13        (b)     
(unused)              0       0     0   5     FB5_14  41    I/O     
(unused)              0       0     0   5     FB5_15  43    I/O     
(unused)              0       0     0   5     FB5_16        (b)     
(unused)              0       0     0   5     FB5_17  44    I/O     
(unused)              0       0     0   5     FB5_18        (b)     
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
(unused)              0       0     0   5     FB6_2   135   I/O     
(unused)              0       0     0   5     FB6_3   136   I/O     
(unused)              0       0     0   5     FB6_4         (b)     
(unused)              0       0     0   5     FB6_5   137   I/O     
(unused)              0       0     0   5     FB6_6   138   I/O     
(unused)              0       0     0   5     FB6_7         (b)     
(unused)              0       0     0   5     FB6_8   139   I/O     
(unused)              0       0     0   5     FB6_9         (b)     
(unused)              0       0     0   5     FB6_10  140   I/O     
(unused)              0       0     0   5     FB6_11        (b)     
(unused)              0       0     0   5     FB6_12        (b)     
(unused)              0       0     0   5     FB6_13        (b)     
(unused)              0       0     0   5     FB6_14  142   I/O     
(unused)              0       0     0   5     FB6_15  143   GSR/I/O 
(unused)              0       0     0   5     FB6_16        (b)     
(unused)              0       0     0   5     FB6_17        (b)     
(unused)              0       0     0   5     FB6_18        (b)     
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB7_1         (b)     
(unused)              0       0     0   5     FB7_2         (b)     
(unused)              0       0     0   5     FB7_3   45    I/O     
(unused)              0       0     0   5     FB7_4         (b)     
(unused)              0       0     0   5     FB7_5   46    I/O     
(unused)              0       0     0   5     FB7_6         (b)     
(unused)              0       0     0   5     FB7_7         (b)     
(unused)              0       0     0   5     FB7_8         (b)     
(unused)              0       0     0   5     FB7_9         (b)     
(unused)              0       0     0   5     FB7_10        (b)     
(unused)              0       0     0   5     FB7_11        (b)     
(unused)              0       0     0   5     FB7_12  48    I/O     
(unused)              0       0     0   5     FB7_13        (b)     
(unused)              0       0     0   5     FB7_14        (b)     
(unused)              0       0     0   5     FB7_15  49    I/O     
(unused)              0       0     0   5     FB7_16        (b)     
(unused)              0       0     0   5     FB7_17        (b)     
(unused)              0       0     0   5     FB7_18        (b)     
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB8_1         (b)     
(unused)              0       0     0   5     FB8_2   130   I/O     
(unused)              0       0     0   5     FB8_3   131   I/O     
(unused)              0       0     0   5     FB8_4         (b)     
(unused)              0       0     0   5     FB8_5   132   I/O     
(unused)              0       0     0   5     FB8_6         (b)     
(unused)              0       0     0   5     FB8_7         (b)     
(unused)              0       0     0   5     FB8_8   133   I/O     
(unused)              0       0     0   5     FB8_9         (b)     
(unused)              0       0     0   5     FB8_10  134   I/O     
(unused)              0       0     0   5     FB8_11        (b)     
(unused)              0       0     0   5     FB8_12        (b)     
(unused)              0       0     0   5     FB8_13        (b)     
(unused)              0       0     0   5     FB8_14        (b)     
(unused)              0       0     0   5     FB8_15        (b)     
(unused)              0       0     0   5     FB8_16        (b)     
(unused)              0       0     0   5     FB8_17        (b)     
(unused)              0       0     0   5     FB8_18        (b)     
*********************************** FB9  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB9_1         (b)     
(unused)              0       0     0   5     FB9_2   50    I/O     
(unused)              0       0     0   5     FB9_3   51    I/O     
(unused)              0       0     0   5     FB9_4         (b)     
(unused)              0       0     0   5     FB9_5   52    I/O     
(unused)              0       0     0   5     FB9_6   53    I/O     
(unused)              0       0     0   5     FB9_7         (b)     
(unused)              0       0     0   5     FB9_8   54    I/O     
(unused)              0       0     0   5     FB9_9         (b)     
(unused)              0       0     0   5     FB9_10        (b)     
(unused)              0       0     0   5     FB9_11  56    I/O     
(unused)              0       0     0   5     FB9_12  57    I/O     
(unused)              0       0     0   5     FB9_13        (b)     
(unused)              0       0     0   5     FB9_14  58    I/O     
(unused)              0       0     0   5     FB9_15        (b)     
(unused)              0       0     0   5     FB9_16        (b)     
(unused)              0       0     0   5     FB9_17  59    I/O     
(unused)              0       0     0   5     FB9_18        (b)     
*********************************** FB10 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB10_1        (b)     
(unused)              0       0     0   5     FB10_2  117   I/O     
(unused)              0       0     0   5     FB10_3  118   I/O     
(unused)              0       0     0   5     FB10_4        (b)     
(unused)              0       0     0   5     FB10_5  119   I/O     
(unused)              0       0     0   5     FB10_6  120   I/O     
(unused)              0       0     0   5     FB10_7        (b)     
(unused)              0       0     0   5     FB10_8  121   I/O     
(unused)              0       0     0   5     FB10_9        (b)     
(unused)              0       0     0   5     FB10_10 124   I/O     
(unused)              0       0     0   5     FB10_11 125   I/O     
(unused)              0       0     0   5     FB10_12 126   I/O     
(unused)              0       0     0   5     FB10_13       (b)     
(unused)              0       0     0   5     FB10_14 128   I/O     
(unused)              0       0     0   5     FB10_15       (b)     
(unused)              0       0     0   5     FB10_16       (b)     
(unused)              0       0     0   5     FB10_17 129   I/O     
(unused)              0       0     0   5     FB10_18       (b)     
*********************************** FB11 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB11_1        (b)     
(unused)              0       0     0   5     FB11_2        (b)     
(unused)              0       0     0   5     FB11_3  60    I/O     
(unused)              0       0     0   5     FB11_4        (b)     
(unused)              0       0     0   5     FB11_5  61    I/O     
(unused)              0       0     0   5     FB11_6        (b)     
(unused)              0       0     0   5     FB11_7        (b)     
(unused)              0       0     0   5     FB11_8        (b)     
(unused)              0       0     0   5     FB11_9        (b)     
(unused)              0       0     0   5     FB11_10 64    I/O     
(unused)              0       0     0   5     FB11_11 66    I/O     
(unused)              0       0     0   5     FB11_12 68    I/O     
(unused)              0       0     0   5     FB11_13       (b)     
(unused)              0       0     0   5     FB11_14 69    I/O     
(unused)              0       0     0   5     FB11_15       (b)     
(unused)              0       0     0   5     FB11_16       (b)     
(unused)              0       0     0   5     FB11_17 70    I/O     
(unused)              0       0     0   5     FB11_18       (b)     
*********************************** FB12 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB12_1        (b)     
(unused)              0       0     0   5     FB12_2  110   I/O     
(unused)              0       0     0   5     FB12_3  111   I/O     
(unused)              0       0     0   5     FB12_4        (b)     
(unused)              0       0     0   5     FB12_5  112   I/O     
(unused)              0       0     0   5     FB12_6        (b)     
(unused)              0       0     0   5     FB12_7        (b)     
(unused)              0       0     0   5     FB12_8  113   I/O     
(unused)              0       0     0   5     FB12_9        (b)     
(unused)              0       0     0   5     FB12_10 115   I/O     
(unused)              0       0     0   5     FB12_11       (b)     
(unused)              0       0     0   5     FB12_12 116   I/O     
(unused)              0       0     0   5     FB12_13       (b)     
(unused)              0       0     0   5     FB12_14       (b)     
(unused)              0       0     0   5     FB12_15       (b)     
(unused)              0       0     0   5     FB12_16       (b)     
(unused)              0       0     0   5     FB12_17       (b)     
(unused)              0       0     0   5     FB12_18       (b)     
*********************************** FB13 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB13_1        (b)     
(unused)              0       0     0   5     FB13_2  71    I/O     
(unused)              0       0     0   5     FB13_3        (b)     
(unused)              0       0     0   5     FB13_4        (b)     
(unused)              0       0     0   5     FB13_5        (b)     
(unused)              0       0     0   5     FB13_6        (b)     
(unused)              0       0     0   5     FB13_7        (b)     
(unused)              0       0     0   5     FB13_8  74    I/O     
(unused)              0       0     0   5     FB13_9        (b)     
(unused)              0       0     0   5     FB13_10       (b)     
(unused)              0       0     0   5     FB13_11 75    I/O     
(unused)              0       0     0   5     FB13_12       (b)     
(unused)              0       0     0   5     FB13_13       (b)     
(unused)              0       0     0   5     FB13_14 76    I/O     
(unused)              0       0     0   5     FB13_15 77    I/O     
(unused)              0       0     0   5     FB13_16       (b)     
(unused)              0       0     0   5     FB13_17 78    I/O     
(unused)              0       0     0   5     FB13_18       (b)     
*********************************** FB14 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB14_1        (b)     
(unused)              0       0     0   5     FB14_2        (b)     
(unused)              0       0     0   5     FB14_3  100   I/O     
(unused)              0       0     0   5     FB14_4        (b)     
(unused)              0       0     0   5     FB14_5  101   I/O     
(unused)              0       0     0   5     FB14_6  102   I/O     
(unused)              0       0     0   5     FB14_7        (b)     
(unused)              0       0     0   5     FB14_8  103   I/O     
(unused)              0       0     0   5     FB14_9        (b)     
(unused)              0       0     0   5     FB14_10 104   I/O     
(unused)              0       0     0   5     FB14_11 105   I/O     
(unused)              0       0     0   5     FB14_12       (b)     
(unused)              0       0     0   5     FB14_13       (b)     
(unused)              0       0     0   5     FB14_14 106   I/O     
(unused)              0       0     0   5     FB14_15 107   I/O     
(unused)              0       0     0   5     FB14_16       (b)     
(unused)              0       0     0   5     FB14_17       (b)     
(unused)              0       0     0   5     FB14_18       (b)     
*********************************** FB15 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB15_1        (b)     
(unused)              0       0     0   5     FB15_2  79    I/O     
(unused)              0       0     0   5     FB15_3  80    I/O     
(unused)              0       0     0   5     FB15_4        (b)     
(unused)              0       0     0   5     FB15_5        (b)     
(unused)              0       0     0   5     FB15_6        (b)     
(unused)              0       0     0   5     FB15_7        (b)     
(unused)              0       0     0   5     FB15_8  81    I/O     
(unused)              0       0     0   5     FB15_9        (b)     
(unused)              0       0     0   5     FB15_10 82    I/O     
(unused)              0       0     0   5     FB15_11 83    I/O     
(unused)              0       0     0   5     FB15_12 85    I/O     
(unused)              0       0     0   5     FB15_13       (b)     
(unused)              0       0     0   5     FB15_14 86    I/O     
(unused)              0       0     0   5     FB15_15 87    I/O     
(unused)              0       0     0   5     FB15_16       (b)     
(unused)              0       0     0   5     FB15_17 88    I/O     
(unused)              0       0     0   5     FB15_18       (b)     
*********************************** FB16 ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB16_1        (b)     
(unused)              0       0     0   5     FB16_2  91    I/O     
(unused)              0       0     0   5     FB16_3  92    I/O     
(unused)              0       0     0   5     FB16_4        (b)     
(unused)              0       0     0   5     FB16_5  93    I/O     
(unused)              0       0     0   5     FB16_6  94    I/O     
(unused)              0       0     0   5     FB16_7        (b)     
(unused)              0       0     0   5     FB16_8  95    I/O     
(unused)              0       0     0   5     FB16_9        (b)     
(unused)              0       0     0   5     FB16_10 96    I/O     
(unused)              0       0     0   5     FB16_11 97    I/O     
(unused)              0       0     0   5     FB16_12 98    I/O     
(unused)              0       0     0   5     FB16_13       (b)     
(unused)              0       0     0   5     FB16_14       (b)     
(unused)              0       0     0   5     FB16_15       (b)     
(unused)              0       0     0   5     FB16_16       (b)     
(unused)              0       0     0   5     FB16_17       (b)     
(unused)              0       0     0   5     FB16_18       (b)     
*******************************  Equations  ********************************

********** Mapped Logic **********

FDCPE_XLXI_14/Q0: FDCPE port map (XLXI_14/Q(0),XLXI_14/Q_D(0),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(0) <= (XLXN_18(0) AND load/load_D2);

FDCPE_XLXI_14/Q1: FDCPE port map (XLXI_14/Q(1),XLXI_14/Q_D(1),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(1) <= ((XLXN_18(1) AND load/load_D2)
	OR (XLXI_14/Q(0) AND NOT load/load_D2));

FDCPE_XLXI_14/Q2: FDCPE port map (XLXI_14/Q(2),XLXI_14/Q_D(2),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(2) <= ((XLXN_18(2) AND load/load_D2)
	OR (XLXI_14/Q(1) AND NOT load/load_D2));

FDCPE_XLXI_14/Q3: FDCPE port map (XLXI_14/Q(3),XLXI_14/Q_D(3),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(3) <= ((XLXN_18(3) AND load/load_D2)
	OR (XLXI_14/Q(2) AND NOT load/load_D2));

FDCPE_XLXI_14/Q4: FDCPE port map (XLXI_14/Q(4),XLXI_14/Q_D(4),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(4) <= ((XLXN_18(4) AND load/load_D2)
	OR (XLXI_14/Q(3) AND NOT load/load_D2));

FDCPE_XLXI_14/Q5: FDCPE port map (XLXI_14/Q(5),XLXI_14/Q_D(5),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(5) <= ((XLXN_18(5) AND load/load_D2)
	OR (XLXI_14/Q(4) AND NOT load/load_D2));

FDCPE_XLXI_14/Q6: FDCPE port map (XLXI_14/Q(6),XLXI_14/Q_D(6),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(6) <= ((XLXN_18(6) AND load/load_D2)
	OR (XLXI_14/Q(5) AND NOT load/load_D2));

FDCPE_XLXI_14/Q7: FDCPE port map (XLXI_14/Q(7),XLXI_14/Q_D(7),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(7) <= ((XLXN_18(7) AND load/load_D2)
	OR (XLXI_14/Q(6) AND NOT load/load_D2));

FDCPE_XLXI_14/Q8: FDCPE port map (XLXI_14/Q(8),XLXI_14/Q_D(8),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(8) <= ((XLXN_18(8) AND load/load_D2)
	OR (XLXI_14/Q(7) AND NOT load/load_D2));

FDCPE_XLXI_14/Q9: FDCPE port map (XLXI_14/Q(9),XLXI_14/Q_D(9),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(9) <= ((XLXN_18(9) AND load/load_D2)
	OR (XLXI_14/Q(8) AND NOT load/load_D2));

FDCPE_XLXI_14/Q10: FDCPE port map (XLXI_14/Q(10),XLXI_14/Q_D(10),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(10) <= ((XLXN_18(10) AND load/load_D2)
	OR (XLXI_14/Q(9) AND NOT load/load_D2));

FDCPE_XLXI_14/Q11: FDCPE port map (XLXI_14/Q(11),XLXI_14/Q_D(11),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(11) <= ((XLXN_18(11) AND load/load_D2)
	OR (XLXI_14/Q(10) AND NOT load/load_D2));

FDCPE_XLXI_14/Q12: FDCPE port map (XLXI_14/Q(12),XLXI_14/Q_D(12),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(12) <= ((XLXN_18(12) AND load/load_D2)
	OR (XLXI_14/Q(11) AND NOT load/load_D2));

FDCPE_XLXI_14/Q13: FDCPE port map (XLXI_14/Q(13),XLXI_14/Q_D(13),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(13) <= ((XLXN_18(13) AND load/load_D2)
	OR (XLXI_14/Q(12) AND NOT load/load_D2));

FDCPE_XLXI_14/Q14: FDCPE port map (XLXI_14/Q(14),XLXI_14/Q_D(14),clk_spi,'0','0',ce_spi);
XLXI_14/Q_D(14) <= ((XLXN_18(14) AND load/load_D2)
	OR (XLXI_14/Q(13) AND NOT load/load_D2));

FTCPE_XLXN_180: FTCPE port map (XLXN_18(0),'1',clk,reset,'0',XLXN_18_CE(0));
XLXN_18_CE(0) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_181: FTCPE port map (XLXN_18(1),XLXN_18(0),clk,reset,'0',XLXN_18_CE(1));
XLXN_18_CE(1) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_182: FTCPE port map (XLXN_18(2),XLXN_18_T(2),clk,reset,'0',XLXN_18_CE(2));
XLXN_18_T(2) <= (XLXN_18(0) AND XLXN_18(1));
XLXN_18_CE(2) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_183: FTCPE port map (XLXN_18(3),XLXN_18_T(3),clk,reset,'0',XLXN_18_CE(3));
XLXN_18_T(3) <= (XLXN_18(0) AND XLXN_18(1) AND XLXN_18(2));
XLXN_18_CE(3) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_184: FTCPE port map (XLXN_18(4),XLXN_18_T(4),clk,reset,'0',XLXN_18_CE(4));
XLXN_18_T(4) <= (XLXN_18(0) AND XLXN_18(1) AND XLXN_18(2) AND 
	XLXN_18(3));
XLXN_18_CE(4) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_185: FTCPE port map (XLXN_18(5),XLXN_18_T(5),clk,reset,'0',XLXN_18_CE(5));
XLXN_18_T(5) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(1) AND 
	XLXN_18(2) AND XLXN_18(3));
XLXN_18_CE(5) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_186: FTCPE port map (XLXN_18(6),XLXN_18_T(6),clk,reset,'0',XLXN_18_CE(6));
XLXN_18_T(6) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(1) AND 
	XLXN_18(5) AND XLXN_18(2) AND XLXN_18(3));
XLXN_18_CE(6) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_187: FTCPE port map (XLXN_18(7),XLXN_18_T(7),clk,reset,'0',XLXN_18_CE(7));
XLXN_18_T(7) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(1) AND 
	XLXN_18(5) AND XLXN_18(2) AND XLXN_18(6) AND XLXN_18(3));
XLXN_18_CE(7) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_188: FTCPE port map (XLXN_18(8),XLXN_18_T(8),clk,reset,'0',XLXN_18_CE(8));
XLXN_18_T(8) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(1) AND 
	XLXN_18(5) AND XLXN_18(2) AND XLXN_18(6) AND XLXN_18(3) AND 
	XLXN_18(7));
XLXN_18_CE(8) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_189: FTCPE port map (XLXN_18(9),XLXN_18_T(9),clk,reset,'0',XLXN_18_CE(9));
XLXN_18_T(9) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND 
	XLXN_18(1) AND XLXN_18(5) AND XLXN_18(2) AND XLXN_18(6) AND 
	XLXN_18(3) AND XLXN_18(7));
XLXN_18_CE(9) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_1810: FTCPE port map (XLXN_18(10),XLXN_18_T(10),clk,reset,'0',XLXN_18_CE(10));
XLXN_18_T(10) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND 
	XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND XLXN_18(2) AND 
	XLXN_18(6) AND XLXN_18(3) AND XLXN_18(7));
XLXN_18_CE(10) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_1811: FTCPE port map (XLXN_18(11),XLXN_18_T(11),clk,reset,'0',XLXN_18_CE(11));
XLXN_18_T(11) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND 
	XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND XLXN_18(10) AND 
	XLXN_18(2) AND XLXN_18(6) AND XLXN_18(3) AND XLXN_18(7));
XLXN_18_CE(11) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_1812: FTCPE port map (XLXN_18(12),XLXN_18_T(12),clk,reset,'0',XLXN_18_CE(12));
XLXN_18_T(12) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND 
	XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND XLXN_18(10) AND 
	XLXN_18(2) AND XLXN_18(6) AND XLXN_18(11) AND XLXN_18(3) AND 
	XLXN_18(7));
XLXN_18_CE(12) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_1813: FTCPE port map (XLXN_18(13),XLXN_18_T(13),clk,reset,'0',XLXN_18_CE(13));
XLXN_18_T(13) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND 
	XLXN_18(12) AND XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND 
	XLXN_18(10) AND XLXN_18(2) AND XLXN_18(6) AND XLXN_18(11) AND 
	XLXN_18(3) AND XLXN_18(7));
XLXN_18_CE(13) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_1814: FTCPE port map (XLXN_18(14),XLXN_18_T(14),clk,reset,'0',XLXN_18_CE(14));
XLXN_18_T(14) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND 
	XLXN_18(12) AND XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND 
	XLXN_18(10) AND XLXN_18(13) AND XLXN_18(2) AND XLXN_18(6) AND 
	XLXN_18(11) AND XLXN_18(3) AND XLXN_18(7));
XLXN_18_CE(14) <= (XLXN_4 AND NOT XLXN_5);

FTCPE_XLXN_1815: FTCPE port map (XLXN_18(15),XLXN_18_T(15),clk,reset,'0',XLXN_18_CE(15));
XLXN_18_T(15) <= (XLXN_18(0) AND XLXN_18(4) AND XLXN_18(8) AND 
	XLXN_18(12) AND XLXN_18(1) AND XLXN_18(5) AND XLXN_18(9) AND 
	XLXN_18(10) AND XLXN_18(13) AND XLXN_18(2) AND XLXN_18(6) AND 
	XLXN_18(11) AND XLXN_18(14) AND XLXN_18(3) AND XLXN_18(7));
XLXN_18_CE(15) <= (XLXN_4 AND NOT XLXN_5);

FDCPE_XLXN_26: FDCPE port map (XLXN_26,ce_spi,clk_spi,'0','0');

FDCPE_XLXN_4: FDCPE port map (XLXN_4,'0','0',reset,start);

FDCPE_XLXN_5: FDCPE port map (XLXN_5,'0','0',reset,stop);

FDCPE_dat_spi: FDCPE port map (dat_spi,dat_spi_D,clk_spi,'0','0',ce_spi);
dat_spi_D <= ((XLXN_18(15) AND load/load_D2)
	OR (XLXI_14/Q(14) AND NOT load/load_D2));


load/load_D2 <= (ce_spi AND NOT XLXN_26);

FDCPE_reset: FDCPE port map (reset,load/load_D2,clk_spi,'0','0');

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95288XL-10-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCC                           
  2 KPR                              74 KPR                           
  3 KPR                              75 KPR                           
  4 KPR                              76 KPR                           
  5 KPR                              77 KPR                           
  6 KPR                              78 KPR                           
  7 KPR                              79 KPR                           
  8 VCC                              80 KPR                           
  9 KPR                              81 KPR                           
 10 KPR                              82 KPR                           
 11 KPR                              83 KPR                           
 12 KPR                              84 VCC                           
 13 KPR                              85 KPR                           
 14 KPR                              86 KPR                           
 15 KPR                              87 KPR                           
 16 KPR                              88 KPR                           
 17 KPR                              89 GND                           
 18 GND                              90 GND                           
 19 KPR                              91 KPR                           
 20 KPR                              92 KPR                           
 21 KPR                              93 KPR                           
 22 KPR                              94 KPR                           
 23 KPR                              95 KPR                           
 24 KPR                              96 KPR                           
 25 KPR                              97 KPR                           
 26 KPR                              98 KPR                           
 27 KPR                              99 GND                           
 28 ce_spi                          100 KPR                           
 29 GND                             101 KPR                           
 30 clk                             102 KPR                           
 31 dat_spi                         103 KPR                           
 32 clk_spi                         104 KPR                           
 33 start                           105 KPR                           
 34 stop                            106 KPR                           
 35 KPR                             107 KPR                           
 36 GND                             108 GND                           
 37 VCC                             109 VCC                           
 38 KPR                             110 KPR                           
 39 KPR                             111 KPR                           
 40 KPR                             112 KPR                           
 41 KPR                             113 KPR                           
 42 VCC                             114 GND                           
 43 KPR                             115 KPR                           
 44 KPR                             116 KPR                           
 45 KPR                             117 KPR                           
 46 KPR                             118 KPR                           
 47 GND                             119 KPR                           
 48 KPR                             120 KPR                           
 49 KPR                             121 KPR                           
 50 KPR                             122 TDO                           
 51 KPR                             123 GND                           
 52 KPR                             124 KPR                           
 53 KPR                             125 KPR                           
 54 KPR                             126 KPR                           
 55 VCC                             127 VCC                           
 56 KPR                             128 KPR                           
 57 KPR                             129 KPR                           
 58 KPR                             130 KPR                           
 59 KPR                             131 KPR                           
 60 KPR                             132 KPR                           
 61 KPR                             133 KPR                           
 62 GND                             134 KPR                           
 63 TDI                             135 KPR                           
 64 KPR                             136 KPR                           
 65 TMS                             137 KPR                           
 66 KPR                             138 KPR                           
 67 TCK                             139 KPR                           
 68 KPR                             140 KPR                           
 69 KPR                             141 VCC                           
 70 KPR                             142 KPR                           
 71 KPR                             143 KPR                           
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95288xl-10-TQ144
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25