[Warning]:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'first_project_top.ise'.INFO:Cpld - Inferring BUFG constraint for signal 'clk' based upon the LOC constraint 'P30'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored.INFO:Cpld - Inferring BUFG constraint for signal 'clk_spi' based upon the LOC constraint 'P32'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. |
[Warning]:Cpld:310 - Cannot apply TIMESPEC TS_clk_spi = PERIOD:clk_spi:500.000nS:HIGH:250.000nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. |
[Warning]:Cpld:310 - Cannot apply TIMESPEC TS_clk_100 = PERIOD:clk_100:10.000nS:HIGH:5.000nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC. |