first_project_top_first_project_top_sch_tb Project Status
Project File: first_project.xise Parser Errors: No Errors
Module Name: first_project_top Implementation State: Fitted
Target Device: xc95288xl-10TQ144
  • Errors:
 
Product Version:ISE 13.2
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentÑá 5. ÿíâ 18:49:07 2013   
Translation ReportCurrentÑá 5. ÿíâ 18:49:13 2013000
CPLD Fitter Report (Text)CurrentÑá 5. ÿíâ 18:49:17 201301 Warning (1 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Fit Simulation Model Report  

Date Generated: 01/12/2013 - 15:08:12