first_project_top Project Status (01/05/2013 - 18:49:22) | |||
Project File: | first_project.xise | Parser Errors: | No Errors |
Module Name: | first_project_top | Implementation State: | Synthesized |
Target Device: | xc95288xl-10TQ144 |
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Product Version: | ISE 13.2 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Ñá 5. ÿíâ 19:10:47 2013 | ||||
Translation Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Ñá 12. ÿíâ 16:13:43 2013 | |
Post-Fit Simulation Model Report |