first_project_top Project Status (01/05/2013 - 18:49:22)
Project File: first_project.xise Parser Errors: No Errors
Module Name: first_project_top Implementation State: Synthesized
Target Device: xc95288xl-10TQ144
  • Errors:
 
Product Version:ISE 13.2
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentÑá 5. ÿíâ 19:10:47 2013   
Translation Report     
CPLD Fitter Report (Text)     
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentÑá 12. ÿíâ 16:13:43 2013
Post-Fit Simulation Model Report  

Date Generated: 01/13/2013 - 15:07:57